Physics Colloquium - Professor Yehuda Braiman

Abstract

Designing fast and energy efficient memories is considered as very important and yet unsolved challenge for future beyond Moore exascale and quantum computing. One of the major technologies considered for such memories is technology based on superconducting Josephson junctions. While superconducting single flux quantum (SFQ) digital logic circuits show promise to significantly advance performance in variety of applications, designing random access memory (RAM) for superconducting circuits still poses a significant challenge. A variety of designs have been proposed including memories based on single flux quantum digital logic, hybrid superconducting CMOS designs, magnetic Josephson junction RAMS, and others. Some of the main challenges (and also expectations) in developing superconducting memory are significantly reducing power dissipation, increasing access speed, and also reducing the size of the chip.

In our talk, we will review the current state of the art of cryogenic memory designs and will present our proposed memory cell design that is based on the dynamics of small coupled arrays of Josephson junctions. In such a design, write, read, and reset operations can be executed on the same basic circuit. The operating principles of the proposed design refer to the existence of multiple stable states that may exist in coupled nonlinear arrays of Josephson junctions. Multiple states in a Josephson junction array can be simultaneously stable, and transitions between these states can be achieved by incrementally varying accessible parameters of the system or by applying an external pulse. Write, read, and reset operations may be executed from the same or different junctions, depending on the mode of operation. When no memory operations (read, write, reset) are implemented in the circuit, the voltage of each junction is zero and consequently energy dissipation is minimal (energy will dissipate mainly at the time of memory access operations). Moreover, if the circuit operation mode and parameter set are chosen appropriately then both memory access times and energies can be simultaneously minimized. The proposed memory cell design allows for multivalued memory operations and recently we have demonstrated operation of ternary memory cells.

Our proposed cryogenic memory cell circuits were recently fabricated and tested. Experimental results show excellent resemblance with the presented memory cell operational logic and also show an excellent fit with WRspice simulations of the memory cell circuit that includes memory cell and all the circuit peripherals.