Patterning at the Nanoscale: Designing Materials and Processes to Enable Nanolithography Clifford L. Henderson School of Chemical Engineering, Georgia Institute of Technology The meteoric rise in the functionality of semiconductor integrated circuits (IC¡¦s) over the past 30 years has dramatically changed human lifestyles and living standards around the world. The number of transistor elements in IC¡¦s has been doubling approximately every 18 months since the early 1970¡¦s (Moore¡¦s Law-see Figure 1) and the computational power of such devices has been increasing even faster. Society has come to heavily rely on this continuous increase in computing power, and the health of a large number of electronics industries depends on the continuation of this trend. Alarmingly, the semiconductor industry today faces a significant number of technological roadblocks that threaten to halt such further advancements, and thus threaten the technologies and economies that rely on semiconductor technology. This possibility has staggering implications for the technological and economic future of both the United States and the world. One of the primary challenges moving forward will be designing ways to continue to create the small patterns (already <150 nm in size) which define the microelectronic device features. The process used to define these nanometer length scale patterns is referred to as microlithography. Currently optical lithography using ultraviolet light is used to pattern semiconductor devices, but there are significant roadblocks for the extension of this technology to feature sizes below 100 nm. This seminar will provide a brief introduction to microelectronics fabrication and microlithography in general. Specifically, the major challenges and options for future lithographic technologies will be discussed as a motivation for some of the work currently in progress in our research group. One of the critical challenges to be faced in designing new lithographic patterning technologies is the development of new photoresist materials. The first part of this talk will discuss our recent work on understanding the polymer chemistry and physics that control the development of new resist polymers for 157 nm lithography. The other trend occurring as feature sizes decrease is that the film thickness of the photoresist films used for lithographic patterning are also approaching 200 nm and below. This nanometer scale confinement of the polymeric photoresist film also has a strong impact on the physical properties of the film which can affect its lithographic performance. The second part of this talk will talk about our recent work in understanding the impact of nanometer scale confinement in polymer films on their physical properties. Figure 1: Progression of DRAM memory devices showing memory capacity in bytes (left half of boxes), minimum feature size in nanometers (right half of boxes), and the associated lithographic technologies used to produce each generation.